The present invention relates generally to semiconductor devices, and more particularly, to a structure and method for forming one or more spacers in field effect transistor devices without causing insulation gouging or a spacer foot.
A fin field effect transistor (FinFET) provides solutions to metal-oxide-semiconductor field effect transistor (MOSFET) scaling problems at and below, for example, the 22 nm node of semiconductor technology. A FinFET comprises at least one narrow semiconductor fin gated on at least two sides. FinFET structures have conventionally been formed in either a semiconductor on insulator (SOI) substrate or a bulk semiconductor substrate.
A spacer may be formed adjacent to a gate of a FinFET. In a conventional spacer formation process, spacer material may be deposited on a sidewall of a gate and a sidewall of a fin. Some of the spacer material may then be removed from the sidewall of the fin while leaving the spacer on the sidewall of the gate. Typically, this process requires the gate to be substantially taller than the fin so that spacer material may be “pulled down” from the fin sidewalls by a directional etch without completely removing the spacer material from a sidewall of the gate.
However, the spacer pulldown process may result in significant gouging into an underlying substrate between fins. Gouging into the underlying substrate may lead to undesirable defects in a FinFET device, including mechanical instability of the fins, electrical shorting to the substrate, epitaxial defects in a source-drain, and additional parasitic capacitance between the source-drain and the channel. Gouging into an underlying substrate may be reduced by decreasing spacer pulldown, but this may result in residual spacer material left on fin sidewalls. Spacer material residue on fin sidewalls may cause issues in the subsequent fabrication processes such as source-drain epitaxy on the fin sidewalls.